Method for forming via hole having fine hole land

ABSTRACT

A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. divisional application filed under 35 USC1.53(b) claiming benefit of U.S. Ser. No. 11/484,708 filed in the UnitedStates on Jul. 12, 2006, which claims earlier benefit of Korean PatentApplication No. 10-2005-0121752 filed in Korea on Dec. 12, 2005, thecontents of which are hereby incorporated by reference.

FIELD

The present invention relates to a via hole and a method for forming thesame. More particularly, the present invention relates to a via-holehaving a fine hole land, with which the density of circuit patterns canbe increased, and a method for forming the same.

BACKGROUND

With the recent evolution of electronics to slimness, lightness and highperformance and with the rapid increase in the application of built-upPCBs (printed circuit boards) to light, slim and small electronicproducts including wireless communication terminals, digital camcorders,mobile computers, etc., multilayer PCBs are very extensively used.

Multilayer PCBs enable interconnections to be achieved threedimensionally as well as in planes. Particularly, multilayer PCBs canimprove the integration of functional devices, such as ICs (integratedcircuit), LSICs (large scale integrated circuit), etc., allowingelectronic products to have slimness, lightness, and high performance,to achieved structural integration of electric functions and to beproduced in a significantly reduced assembly time period and at a lowcost.

Almost all the built-up PCBs employed in such applications havevia-holes through which interlayer connection is achieved. The recenttendency toward slimness and lightness is causing laser drills to be thenew rising technology used for the formation of the via-holes.

Via-holes, corresponding to passageways for interlayer electricconnection, were conventionally formed using mechanical drills. However,mechanical drilling results in too large a hole to form fine circuits,in addition to increasing the production cost. Nowadays, laser drillingis preferred.

Generally representative of new, smaller vias, called “microvias”, ablind via is drilled from the surface of a PCB and terminates within thesubstrate.

If the cross-sectional area that a via occupies decreases, the abilityto utilize vias increases by a similar amount.

However, the reduction of via size to microvia size means thatmechanical drilling is of no commercial use, implying the generalizationof some alternative processes, such as removal by way of laser orplasma.

The removal of material is the result of an electrochemical reaction tolaser pulse or plasma treatment, which is different from a cuttingaction or treatment. However, removal processes similar to laser pulseor plasma treatment eliminate materials around the central line as well.

Because it primarily results in round holes, such removal, whether usinglaser, plasma, or others, competes with mechanical drilling. Theformation of the round holes is often called ‘drilling’ due to theremoval of materials around the central line, and is thus termed “microvia drilling”.

With reference to FIGS. 1A to 1D, the formation of via-holes in a PCBusing a conventional laser drilling process is schematically shown in astepwise manner.

The conventional method for forming via holes in a PCB by laserdrilling, as shown in FIGS. 1A to 1D, comprises a laser drillingprocess, a desmearing and copper plating process, and a circuitpatterning process.

The formation of via holes in a PCB starts with the drilling of a copperclad laminate 101 of FIG. 1A to form via holes 102 which travel throughtwo layers, as shown in FIG. 1B.

Next, as shown in FIG. 1 C, a desmearing process is conducted,immediately followed by plating the inner walls of the holes with copperto form a copper-plated layer 103.

Subsequently, the copper-plated layer 103 is patterned to form acircuit.

As a rule, the via holes 102 require hole lands for electricalinterconnection. However, the hole lands of via holes act as hindrancesto the increase of the degree of integration of circuit patterns.Referring to FIG. 2A, which shows conventional via-holes in a plan view,hole lands 104 a-104 c prevent circuit lines 105 a-105 c from beingarranged near each other. As shown in FIG. 2A, although the via holesare disposed in a zigzag manner in order to reduce the distance betweencircuit lines 105 a-105 c, the hole lands 104 a-104 c still interferewith the approach of the circuit line 105 a-105 c to each other.

FIG. 2B is a perspective view showing a via hole according to aconventional technology. The via hole, as shown in FIG. 2B, comprises ahole inner wall 107 associated with an upper hole land 104 u at itsupper portion and with a down hole land 104 d at its lower portion. Theupper hole land 104 u is extended through a circuit line 105 to a wirebonding pad while the down hole land 104 d is associated with a solderball pad 108. As can be seen, the hole lands 104 u and 104 d stilloccupy large areas.

SUMMARY

Therefore, it is an object of the present invention to provide a viahole having a fine hole land with which circuit patterns can beconstructed at a high density, and a method for forming the same.

In accordance with an aspect of the present invention, provided is a viahole having a fine hole land, comprising a first conductive layer formedon an inner wall in contact with an insulation layer; a secondconductive layer outside the first conductive layer; and a circuit line,formed on the insulation layer, connecting to the second conductivelayer, wherein the hole land is formed by the first and the secondconductive layer.

In a preferable embodiment, the first conductive layer is extended overthe insulating layer.

In another preferable embodiment, the first layer is an electrolessplated layer.

In a further preferable embodiment, the second conductive layer is anelectroplated layer.

In accordance with another aspect of the present invention, provided isa method for forming a via hole having a fine hole land, comprising:step 1 of forming a via hole in a copper clad laminate, coating anetching resist over the copper clad laminate, and forming a circuitpattern on the copper foil of the copper clad laminate; step 2 offorming a seed layer, coating a photoresist, and exposing an inner wallof the via hole; and step 3 of forming a plated layer on the inner wallof the via hole and removing the photoresist and the seed layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The application of the preferred embodiments of the present invention isbest understood with reference to the accompanying drawings, in whichlike reference numerals are used for like and corresponding parts,wherein:

FIGS. 1A to 1D are schematic views showing conventional processes offorming via holes in a printed circuit board using a laser drill;

FIGS. 2A and 2B are a plan view and a perspective view, respectively,showing via holes formed according to the conventional processes;

FIGS. 3A and 3B are a perspective view and a plan view, respectively,showing a via hole having a fine hole land in accordance with thepresent invention;

FIGS. 4A to 4R are schematic views showing processes of forming a viahole having a fine hole land in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Below, a detailed description is given of an embodiment of the presentinvention with reference to the accompanying drawings.

A via-hole having a fine hole land in accordance with an embodiment ofthe present invention is shown in the perspective view of FIG. 3A whileFIG. 3B. shows the arrangement of a plurality of the via holes in a planview.

In accordance with the present invention, a via hole having a fine holeland comprises a conductive inner wall layer 207, an upper hole land 204u (consisting of 204 ui and 204 uo), a down hole land 204 d (consistingof 204 di and 204 do), a wire bonding pad 206, a solder ball pad 208,and a circuit line 205 for connecting the wire bonding pad 206 with theupper hole land 204 u, as shown in FIG. 3A.

The hole land 204 u is as large as the conductive inner wall layer 207and is divided into an inner hole land 204 ui and an outer hole land 204uo, which extends from the inner hole land 204 ui. Preferably, the outerhole land 204 uo ranges in thickness from 0 to 15 gm. The inner holeland 204 ui has a thickness of 10 pm. Although they are made from thesame material, that is, copper, the inner hole land 204 ui and the outerhole land 204 uo are different in crystalline structure from each otherbecause different processes are used. Specifically, the inner hole land204 ui is electroplated with copper while the outer hole land 204 uoconsists of an electroless copper plated layer and electro-copper platedlayer.

FIG. 3B shows the arrangement of a plurality of the via holes having thefine hole lands 204 ui and 204 uo in a plan view. As shown in FIG. 3B,the thinness of the outer hole lands 204 uoa to 204 uoc allows circuitlines 205 a to 205 c to be disposed closely adjacent to each other,increasing the degree of integration of the circuit patterns.

With reference to FIGS. 4A to 4R, a method of forming a via hole inaccordance with an embodiment of the present invention is illustrated ina stepwise manner.

First, as shown in FIG. 4A, a copper clad laminate 410 comprising aninsulation layer 411 with respective copper layers 412 a and 412 bformed on opposite faces thereof is provided.

The insulation layer 411 is based on resin. Resinous materials show highinsulation properties, but suffer from the disadvantage of being poor inmechanical strength and being dimensionally more unstable in response totemperature change than metallic materials. In order to overcome thedisadvantages, paper, glass fiber, or glass non-woven fabric is used asa reinforcement. The reinforcement increases the strength of theresinous material in both widthwise and lengthwise directions anddecreases the dimensional change with temperature.

The copper clad laminate 410, although shown having copper layers 412 aand 412 b on opposite faces thereof, may comprise only one copper layer.

FIG. 4B is a schematic cross sectional view after the copper cladlaminate (410) is drilled to form via holes 420.

As currently available technologies for forming via holes in PCBs, thereare excimer, Nd:YAG and CO2 laser drilling processes.

Excimer laser is not applied to PCBs. A YAG laser using 355 nm can drillthrough the copper layer, but is 90% reflected by glass epoxy, which maybe used in a prepreg form for the insulation layer.

In contrast, a CO2 laser of 9.4 μm can be applied for drilling thecopper clad laminate because it is absorbed in an amount of 80%.

Afterward, as shown in FIG. 4C, etching resists 430 a, 430 b are formedon either or both surfaces of the copper clad laminate 410 having thevia holes 420 therein. The formation of the etching resists can beachieved in a photographic process or a screen printing process. For thephotographic process, a dry film may be an etching resist, as in a D/Fmethod, or a liquid photosensitive material may be used.

FIG. 4D is a cross sectional view after an image forming process isconducted to form a pattern of the etching resists 430 a, 430 b on thecopper layers 412 a, 412 b, respectively and an etchant is sprayed toremove the copper layer 412 a, 412 b from predetermined areas, with thepattern of the etching resists serving as a mask. The resulting copperclad laminate 410 is shown in the plan view of FIG. 4E and in the rearview of FIG. 4F. As shown in FIG. 4E, a circuit line 435 a extends intothe via hole 420. In addition, a circuit line 435 b is formed on thelower surface of the copper clad laminate 410 so as to extend into orover the via hole 420, as shown in FIG. 4F.

Subsequently, as shown in FIG. 4G, copper plating is conducted to form aseed layer 440. The resulting copper clad laminate 410 is shown in theplan view of FIG. 4H and in the rear side view of FIG. 4I. For thecopper plating, electroless plating (or sputter) is performed prior toelectroplating. The seed layer 440 preferably has a thickness from 0.5to 1.5 μm.

Electroless copper plating (or sputtering) is a technique for providingconductivity for insulators such as resins, ceramics, glass, etc.Performed in such a way that a substrate is immersed in a platingsolution, electroless copper plating allows all parts of the substrate,including the inner wall of the hole, to be plated with copper. By thiselectroless copper plating, called primary copper plating, the uppercopper layer is electrically connected with the lower copper layer. Theprimary copper plating results in a preliminary thin coat for subsequentelectroplating. Due to poor physical properties, the electroless platedcopper coat must be overcoated with copper through electroplating.

The electric conductivity imparted to the inner wall of the hole byelectroless copper plating enables electroplating to be applied thereto.The copper coat formed by electroplating is much thicker and exhibitsbetter physical properties than the copper coat formed by electrolessplating.

Subsequently, as shown in FIG. 4J, a photoresist 450 a, 450 b isselectively formed over the copper clad laminate 410 in such a way thatonly the inner wall of the via hole 420 is exposed. The photoresist 450a, 450 b can be formed using a photographic method or a screen printingmethod. For the photographic method, a dry film may be used as anetching resist, as in a D/F method, or a liquid photosensitive materialmay be used.

Afterwards, an image forming process is performed to remove the part ofthe photoresist 450 a, 450 b corresponding to the via hole 420 to exposethe inner wall of the via hole 420. The resulting structure of thecopper clad laminate 410 is shown in the plan view of FIG. 4K and in arear side view of FIG. 4L. As shown in both FIGS. 4K and 4L, only theinner wall of the via hole 420 is exposed.

FIG. 4M is a cross sectional view after a copper coat is formed on theinner wall of the via hole 420 with the seed layer 440 serving as aplating bar. Preferably, the copper coat 460 has a thickness of 10 .tmor greater. A 10 μm thick or thicker copper coat 460 assures reliableelectric conduction between the upper and the lower layers.

The resulting structure of the copper clad laminate, in which the coppercoat 460 is formed on the inner wall of the via hole 420, is shown inthe plan view of FIG. 4N and in the rear side view of FIG. 4O.

With reference to FIGS. 4N and 4O, the relatively thin seed layer 440 isformed on the inner wall of the via hole 420 while being coated with therelatively thick copper layer 460.

Thereafter, as shown in FIG. 4P, the photoresist 450 a, 450 b is peeledoff and the seed layer is removed by flash etching so as to form acircuit.

Then, a photo solder resist process and subsequent processes areconducted as usual.

As described hereinbefore, the present invention can decrease the areaoccupied by hole lands so as to increase the density of via holes,thereby realizing slimness of the PCB.

That is, the present invention increases the number of circuit lines perunit area, thus increasing the density of circuit patterns.

In addition, the present invention can be applied to the slimness of allelectronic appliances which require fine patterns.

Examples are described in terms of the preferred embodiment of presentinvention. However, it should be understood that such disclosure is notlimited to the explicit description of the present invention. Thedescription and the claims of present invention are to be interpreted ascovering all alterations and modifications within the true scope of thisinvention.

1. A method for forming a via hole having a fine hole land, comprising:(a) forming a via hole in a copper clad laminate, coating an etchingresist over the copper clad laminate, and forming a circuit pattern onthe copper foil of the copper clad laminate; (b) forming a seed layer,coating a photoresist, and exposing an inner wall of the via hole; and(c) forming a plated layer on the inner wall of the via hole andremoving the photoresist and the seed layer.
 2. The method as set forthin claim 1, wherein operation (a) comprises; forming the via hole in thecopper clad laminate using a drilling process; coating an etching resistin a circuit pattern over the copper clad laminate in a circuit pattern;and forming a circuit pattern using an exposure process.
 3. The methodas set forth in claim 1, wherein operation (b) comprises: forming theseed layer using an electroless plating process and an electroplatingprocess; layering the photoresist on the seed layer; and exposing theinner wall of the via hole through an exposure and development processwith the photoresist serving as a mask.
 4. The method as set forth inclaim 3, wherein the seed layer is 1.5 μm thick.
 5. The method as setforth in claim 1, wherein operation (c) comprises: forming a copperlayer on the inner wall of the via hole with the seed layer serving as aplating bar; removing the photoresist; and removing the seed layer byflash etching.
 6. The method as set forth in claim 5, wherein the copperlayer has a thickness of 15 μm or greater.
 7. The method as set forth inclaim 1, further comprising operation (d) of exposing a circumference ofthe via hole, wherein the circumference of the via hole is plated uponthe formation of the plated layer on the inner wall of the via hole inoperation (c).